The present disclosure relates to the field of memory and more particularly to the field of static random-access memory (SRAM).
SRAM is a type of semiconductor memory that includes a plurality of SRAM cells each using bistable latching circuitry to store a bit. SRAM is referred to as static in order to differentiate it from dynamic random-access memory (DRAM). DRAM has to be periodically refreshed in contrary to SRAM which exhibits data remanence. However, SRAM is still volatile in the sense that data is eventually lost when the SRAM is not powered anymore. A variety of SRAM types are known utilizing cells that include different number of transistors, e.g. 4, 6, 8, 10 (4T, 6T, 8T, 10T SRAM), or more transistors per cell. A 6T SRAM may for example utilize six metal-oxide semiconductor field-effect transistors (MOSFETs) per cell to store each memory bit. More precisely, each bit may be stored on four transistors that form a storage element comprising two cross-coupled inverters each of which is formed by two transistors. Two additional access transistors may serve to control access to the cell during read and/or write operations. The respective 6T memory cell has two stable states that are denoted logical ‘0’ and logical ‘1’.
Access to a typical 6T SRAM cell is facilitated by one or more wordlines that control the two access transistors which, in turn, control whether the cell is coupled to one or more bitlines. The SRAM cells or simply cells of an SRAM array or simply memory array may be organized into a matrix form comprising m columns and n rows. A row comprising m cells represents an m-bit word. All cells in a row may be electrically conductive connected to a common wordline for selecting the respective row by addressing the wordline. For reading data from and writing data to the cells of an SRAM array, all cells of a column may be electrically conductive connected to a common pair of bitlines, i.e. a bitline true and a bitline complement. During a read operation, the bit value stored in the memory cell is typically read using both bitlines of the respective pair of bitlines in order to improve noise margins: via the bitline true (blt) the bit value is read, while its inverse value is read via the bitline complement. By selecting a wordline, each of the m bits of a word formed by a row connected with the selected wordline may be synchronously read from or written to a cell of the row via the bit lines connected to the respective cell.
An SRAM cell has three different states: standby, reading, and writing. In a standby state, an SRAM is idle. In a reading state, data has been requested from the SRAM. In a writing state, contents of the SRAM are updated. For a read or write access to an SRAM cell the wordline(s) of the respective cell are asserted initiating the access transistor(s) to connect the SRAM cell to bitline(s). If wordlines are not asserted, access transistors disconnect the SRAM cell from bitlines. In this case, the two cross-coupled inverters continue to reinforce each other as long as they are connected to a power supply.
High-speed memory access has become increasingly important to the overall performance of processors and data processing systems. In general, the read access performance may be critical for the timing performance of an SRAM array, i.e. one of the main contributors to memory latency.